An integrated circuit memory cell is a circuit capable of storing a predetermined number of logic states, most often two logic states. Based on a capacity of retaining or not retaining a memory state under no power conditions, memory cells can be classified as non-volatile or volatile. In particular, a non-volatile (NV) memory cell is capable of retaining its memory state when powered off. In contrast, a volatile memory loses its memory state when powered off.
All integrated circuit non-volatile programmable memory cells include an alterable element that can be altered from a first condition to a second condition, and which retains its second condition even when power is turned off.
The above-described alteration of the alterable element from the first condition to the second condition is usually referred to as programming the memory cell. In some arrangements, the programming is achieved when the alterable element is subjected to specific voltage, current, or voltage-current (power) condition by means of additional supporting circuitry (i.e., a driver). One time programmable non-volatile memory cells (OTP NV) are a type of non-volatile programmable memory cells, for which programming is not reversible.
In a conventional non-volatile programmable memory array having a plurality of non-volatile programmable memory cells, each memory cell has a particular address location, and therefore requires an address decoder circuit plus a write driver circuit and also a read sensing circuit in order to uniquely program (i.e., write) to or read from a respective memory cell.
In some arrangements, address decoding circuits and read sensing circuits can be shared among memory cells. However, write driver circuits are usually not shared among memory cells, and therefore, each memory cell in a memory array has its own write driver circuit. Write driver circuits are known to be physically large, as they are required to have low source resistances at high current levels. Being physically large, write driver circuits tend to limit the number of non-volatile programmable memory cells that can be fabricated into a memory array in an integrated circuit.
In some conventional non-volatile programmable memory arrays having a plurality of non-volatile programmable memory cells, a state of each memory cell, programmed or unprogrammed, is sensed by a respective read sensing circuit.
State detection margin error, power consumption, access time, and silicon area constraints are all tradeoffs that affect the design of read sensing circuits. The requirement for read sensing circuits also tends to limit the number of non-volatile programmable memory cells that can be fabricated in an integrated circuit.
In addition, many types of non-volatile programmable memory cells draw a different amount of current depending upon their logic state. Thus, a conventional non-volatile programmable memory array having a plurality of non-volatile programmable memory cells can draw different amounts of current depending upon the states of memory cells within the memory array and how it is accessed or read. For some electronic systems, this variation may be undesirable.
It would be desirable to have a non-volatile programmable memory cell and an associated non-volatile programmable memory array that can be fabricated with a conventional integrated circuit process and that can achieve a high density of non-volatile programmable memory cells but with a low operational power consumption and a high noise margin state detection.